2.2 KiB
Thingamajig
Thingamajig is a RISC-y and MISC-y homebrew computer architecture. Its git repository can be found at https://ahti.space/git/crazyettin/Thingamajig.
Registers and Memory
- 24-bit instruction register IR
- 16-bit instruction and return pointers IP and RP
- 8-bit general-purpose registers R0-R3
- 8-bit memory addresses 0-FFFF
Multi-byte values are big-endian. Memory addresses FFF0-FFFF are reserved for memory mapped devices; the instruction and return pointers cannot have values higher than FFEF and FFF0 respectively to avoid them. The instruction and return pointers are initialised as 0 and FFF0 respectively, while other registers and memory are unitialised.
Instructions
Instructions without an address argument are 8-bit and those with one 24-bit. The instruction pointer is incremented before being accessed or modified.
0 HALT 1 RET IP = *RP; RP += 2
2 SHL RX RX <<= 1 Logical shifts 3 SHR RX RX >>= 1 4 ROL RX RX <<= 1 Rotating shifts 5 ROR RX RX >>= 1
6 NAND RX, RY RX = ~(RX & RY) 7 AND RX, RY RX &= RY 8 OR RX, RY RX |= RY 9 XOR RX, RY RX ^= RY
A LOAD RX, ADDR RX = *ADDR B STORE RX, ADDR *ADDR = RX Written as "STORE ADDR, RX" in assembly for the sake of consistency.
C BREQ RX, RY, ADDR if (RX == RY) IP = ADDR D BRNEQ RX, RY, ADDR if (RX != RY) IP = ADDR E CLEQ RX, RY, ADDR if (RX == RY) {RP -= 2; *RP = IP; IP = ADDR} F CLNEQ RX, RY, ADDR if (RX != RY) {RP -= 2; *RP = IP; IP = ADDR}
Memory-Mapped Devices
Input (when read from) and output (when written to) are mapped to address FFFF. The emulator emulates a dumb terminal for this.
Arbitrary devices can be mapped to the other reserved addresses.
Initial Program Loader
At boot the initial program loader loads a program to the memory starting from address 0 after which is cedes control to the CPU. The emulator loads the program from a file.