7a606cab32
Waiting for any non-zero duration currently waits for at least one timer cycle (10 ms), which is especially expensive during early boot. The current workaround of simply reading the status 14 times seems really suspicious although the osdev wiki documents it, but let's see how well it works on real hardware, it's probably good enough. Try to determine the initial selected drive to save one drive selection.
909 lines
24 KiB
C++
909 lines
24 KiB
C++
/*
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* Copyright (c) 2011-2016, 2018, 2021, 2022 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* disk/ata/port.cpp
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* Driver for ATA.
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <endian.h>
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#include <timespec.h>
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#include <sortix/clock.h>
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#include <sortix/mman.h>
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#include <sortix/kernel/addralloc.h>
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#include <sortix/kernel/clock.h>
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#include <sortix/kernel/ioport.h>
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#include <sortix/kernel/kthread.h>
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#include <sortix/kernel/log.h>
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#include <sortix/kernel/memorymanagement.h>
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#include <sortix/kernel/signal.h>
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#include <sortix/kernel/time.h>
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#include "hba.h"
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#include "port.h"
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#include "registers.h"
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namespace Sortix {
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namespace ATA {
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static void copy_ata_string(char* dest, const char* src, size_t length)
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{
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for ( size_t i = 0; i < length; i += 2 )
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{
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dest[i + 0] = src[i + 1];
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dest[i + 1] = src[i + 0];
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}
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length = strnlen(dest, length);
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while ( 0 < length && dest[length - 1] == ' ' )
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length--;
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dest[length] = '\0';
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}
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static void sleep_400_nanoseconds(uint16_t port_base)
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{
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// TODO: The clock granularity of 10 ms slows down the early boot.
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#if 0
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struct timespec delay = timespec_make(0, 400);
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Clock* clock = Time::GetClock(CLOCK_BOOTTIME);
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clock->SleepDelay(delay);
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#else
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for ( int i = 0; i < 14; i++ )
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inport8(port_base + REG_STATUS);
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#endif
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}
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Port::Port(Channel* channel, unsigned int port_index)
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{
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this->channel = channel;
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this->port_index = port_index;
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memset(&control_alloc, 0, sizeof(control_alloc));
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memset(&dma_alloc, 0, sizeof(dma_alloc));
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is_control_page_mapped = false;
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is_dma_page_mapped = false;
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interrupt_signaled = false;
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transfer_in_progress = false;
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control_physical_frame = 0;
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dma_physical_frame = 0;
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}
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Port::~Port()
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{
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if ( transfer_in_progress )
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FinishTransferDMA();
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if ( is_control_page_mapped )
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{
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Memory::Unmap(control_alloc.from);
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Memory::Flush();
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}
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if ( is_dma_page_mapped )
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{
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Memory::Unmap(dma_alloc.from);
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Memory::Flush();
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}
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FreeKernelAddress(&control_alloc);
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FreeKernelAddress(&dma_alloc);
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if ( control_physical_frame )
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Page::Put(control_physical_frame, PAGE_USAGE_DRIVER);
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if ( dma_physical_frame )
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Page::Put(dma_physical_frame, PAGE_USAGE_DRIVER);
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}
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void Port::LogF(const char* format, ...)
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{
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// TODO: Print this line in an atomic manner.
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const char* cdesc = channel->channel_index == 0 ? "primary" : "secondary";
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const char* ddesc = port_index == 0 ? "master" : "slave";
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Log::PrintF("ata: pci 0x%X: %s %s: ", channel->devaddr, cdesc, ddesc);
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va_list ap;
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va_start(ap, format);
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Log::PrintFV(format, ap);
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va_end(ap);
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Log::PrintF("\n");
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}
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bool Port::Initialize()
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{
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if ( !(control_physical_frame = Page::Get32Bit(PAGE_USAGE_DRIVER)) )
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{
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LogF("error: control page allocation failure");
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return false;
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}
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if ( !(dma_physical_frame = Page::Get32Bit(PAGE_USAGE_DRIVER)) )
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{
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LogF("error: dma page allocation failure");
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return false;
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}
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if ( !AllocateKernelAddress(&control_alloc, Page::Size()) )
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{
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LogF("error: control page virtual address allocation failure");
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return false;
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}
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if ( !AllocateKernelAddress(&dma_alloc, Page::Size()) )
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{
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LogF("error: dma page virtual address allocation failure");
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return false;
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}
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int prot = PROT_KREAD | PROT_KWRITE;
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is_control_page_mapped =
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Memory::Map(control_physical_frame, control_alloc.from, prot);
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if ( !is_control_page_mapped )
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{
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LogF("error: control page virtual address allocation failure");
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return false;
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}
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Memory::Flush();
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is_dma_page_mapped = Memory::Map(dma_physical_frame, dma_alloc.from, prot);
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if ( !is_dma_page_mapped )
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{
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LogF("error: dma page virtual address allocation failure");
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return false;
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}
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Memory::Flush();
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prdt = (volatile struct prd*) (control_alloc.from);
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return true;
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}
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bool Port::FinishInitialize()
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{
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ScopedLock lock(&channel->hw_lock);
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channel->SelectDrive(port_index);
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// ATAPI can be detected by using the LBA registers after IDENTIFY.
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is_packet_interface = false;
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retry_identify_packet:
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outport8(channel->port_base + REG_COMMAND,
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is_packet_interface ? CMD_IDENTIFY_PACKET : CMD_IDENTIFY);
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sleep_400_nanoseconds(channel->port_base);
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// TODO: The status polling logic should be double-checked against some
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// formal specification telling how this should properly be done.
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uint8_t status = inport8(channel->port_base + REG_STATUS);
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if ( status == 0 )
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{
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// Non-existent.
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return errno = ENODEV, false;
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}
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// TODO: This failing might mean non-existent.
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// TODO: What is a good timeout here?
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if ( !wait_inport8_clear(channel->port_base + REG_STATUS, STATUS_BUSY,
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false, 1000 /*ms*/) )
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{
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// IDENTIFY timed out, still busy.
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return errno = ETIMEDOUT, false;
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}
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// TODO: This failing might mean non-existent.
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// TODO: Should we actually wait here, or are the status set already?
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// TODO: What is a good timeout here?
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if ( !wait_inport8_set(channel->port_base + REG_STATUS,
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STATUS_DATAREADY | STATUS_ERROR, true, 1000 /*ms*/) )
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{
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// IDENTIFY timed out, status not set.
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return errno = ETIMEDOUT, false;
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}
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status = inport8(channel->port_base + REG_STATUS);
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if ( status & STATUS_ERROR )
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{
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uint8_t mid = inport8(channel->port_base + REG_LBA_MID);
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uint8_t high = inport8(channel->port_base + REG_LBA_HIGH);
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if ( (mid == 0x14 && high == 0xEB) || (mid == 0x69 && high == 0x96) )
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{
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if ( is_packet_interface )
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{
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LogF("ignoring: IDENTIFY_PACKET returned error status");
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return errno = EIO, false;
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}
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is_packet_interface = true;
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goto retry_identify_packet;
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}
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else if ( mid == 0x3C && high == 0xC3 )
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{
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// TODO: Does this actually happen and can we do something?
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//LogF("ignoring: found SATA device instead");
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return errno = ENODRV, false;
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}
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else if ( (mid || high) && (mid != 0x7F && high != 0x7F) )
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{
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//LogF("ignoring: found unknown device instead (0x%02X:0x%02X)",
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// mid, high);
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return errno = ENODRV, false;
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}
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else if ( mid == 0x7F && high == 0x7F )
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{
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//LogF("ignoring: non-existent");
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return errno = EIO, false;
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}
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else
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{
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LogF("ignoring: IDENTIFY returned error status");
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return errno = EIO, false;
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}
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}
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for ( size_t i = 0; i < 256; i++ )
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{
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uint16_t value = inport16(channel->port_base + REG_DATA);
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identify_data[2*i + 0] = value >> 0 & 0xFF;
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identify_data[2*i + 1] = value >> 8 & 0xFF;
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}
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little_uint16_t* words = (little_uint16_t*) identify_data;
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if ( !is_packet_interface && (words[0] & (1 << 15)) )
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return errno = EINVAL, false; // Skipping non-ATA device.
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if ( !is_packet_interface && !(words[49] & (1 << 9)) )
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return errno = EINVAL, false; // Skipping non-LBA device.
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copy_ata_string(serial, (const char*) &words[10], sizeof(serial) - 1);
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copy_ata_string(revision, (const char*) &words[23], sizeof(revision) - 1);
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copy_ata_string(model, (const char*) &words[27], sizeof(model) - 1);
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is_using_dma = true;
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// This is apparently the case on older hardware, there are additional
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// restrictions on DMA usage, we could work around it, but instead we just
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// don't use DMA at all, as such hardware should be irrelevant by now. Print
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// a warning so we can look into this if it actually turns out to matter.
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// TODO: Arg. This happens in VirtualBox!
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// TODO: Alternative solution. If this is true, then it should lock the
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// HBA hw_lock instead than the channel one.
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uint8_t bm_status = inport8(channel->busmaster_base + BUSMASTER_REG_STATUS);
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if ( bm_status & BUSMASTER_STATUS_SIMPLEX )
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{
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LogF("warning: simplex silliness: no DMA");
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is_using_dma = false;
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}
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// TODO: Why is this commented out? Due to the above?
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#if 0
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if ( port_index == 0 && !(bm_status & BUSMASTER_STATUS_MASTER_DMA_INIT) )
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{
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LogF("warning: no DMA support");
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is_using_dma = false;
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}
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if ( port_index == 1 && !(bm_status & BUSMASTER_STATUS_SLAVE_DMA_INIT) )
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{
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LogF("warning: no DMA support");
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is_using_dma = false;
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}
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#endif
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if ( is_packet_interface )
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{
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is_lba48 = true;
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block_count = 0;
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block_size = 0;
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cylinder_count = 0;
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head_count = 0;
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sector_count = 0;
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device_size = 0;
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if ( !ReadCapacityATAPI(true) )
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{
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//LogF("ReadCapacityATAPI failed: %m");
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}
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return true;
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}
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this->is_lba48 = words[83] & (1 << 10);
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uint64_t block_count;
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if ( is_lba48 )
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{
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block_count = (uint64_t) words[100] << 0 |
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(uint64_t) words[101] << 16 |
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(uint64_t) words[102] << 32 |
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(uint64_t) words[103] << 48;
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}
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else
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{
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block_count = (uint64_t) words[60] << 0 |
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(uint64_t) words[61] << 16;
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}
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uint64_t block_size = 512;
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if( (words[106] & (1 << 14)) &&
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!(words[106] & (1 << 15)) &&
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(words[106] & (1 << 12)) )
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{
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block_size = 2 * ((uint64_t) words[117] << 0 |
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(uint64_t) words[118] << 16);
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}
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cylinder_count = words[1];
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head_count = words[3];
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sector_count = words[6];
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if ( Page::Size() < block_size )
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{
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LogF("error: block size is larger than page size: %ji", block_size);
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return errno = EINVAL, false;
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}
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if ( __builtin_mul_overflow(block_count, block_size, &device_size) )
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{
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LogF("error: device size overflows off_t");
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return errno = EOVERFLOW, false;
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}
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this->block_count = (blkcnt_t) block_count;
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this->block_size = (blkcnt_t) block_size;
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return true;
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}
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bool Port::ReadCapacityATAPI(bool no_error)
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{
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struct atapi_packet* packet = (struct atapi_packet*) dma_alloc.from;
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memset(packet, 0, sizeof(*packet));
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packet->operation = ATAPI_CMD_READ_CAPACITY;
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struct atapi_capacity* reply = (struct atapi_capacity*) dma_alloc.from;
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if ( !CommandATAPI(sizeof(*reply), no_error) )
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return errno = ENOMEDIUM, false;
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block_count = (blkcnt_t) reply->last_lba + 1;
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block_size = (blkcnt_t) reply->block_size;
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if ( Page::Size() < (uintmax_t) block_size )
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{
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LogF("error: block size is larger than page size: %ji", block_size);
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return errno = EINVAL, false;
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}
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if ( __builtin_mul_overflow(block_count, block_size, &device_size) )
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{
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LogF("error: device size overflows off_t");
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return errno = EOVERFLOW, false;
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}
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return true;
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}
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bool Port::CommandATAPI(size_t response_size, bool no_error)
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{
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outport8(channel->port_base + REG_FEATURE, is_using_dma ? 0x01 : 0x00);
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outport8(channel->port_base + REG_LBA_LOW, 0x08);
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outport8(channel->port_base + REG_LBA_MID, 0x08);
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if ( is_using_dma )
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CommandDMA(CMD_PACKET, response_size, false);
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else
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CommandPIO(CMD_PACKET, response_size, false);
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if ( !TransferPIO(sizeof(struct atapi_packet), true, no_error) )
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{
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if ( !no_error )
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LogF("EIO: %s:%u", __FILE__, __LINE__);
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return errno = EIO, false;
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}
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if ( is_using_dma )
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{
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if ( !FinishTransferDMA() )
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{
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if ( !no_error )
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LogF("EIO: %s:%u", __FILE__, __LINE__);
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return errno = EIO, false;
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}
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}
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else
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{
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// TODO: Read LBA Mid and LBA High to know how many bytes we are
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// expected to transfer.
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if ( !TransferPIO(response_size, false, no_error) )
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{
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if ( !no_error )
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LogF("EIO: %s:%u", __FILE__, __LINE__);
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return errno = EIO, false;
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}
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}
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return true;
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}
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void Port::Seek(blkcnt_t block_index, size_t count)
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{
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uintmax_t lba = (uintmax_t) block_index;
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uint8_t mode = (is_lba48 ? 0x40 : 0xE0) | port_index << 4;
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outport8(channel->port_base + REG_DRIVE_SELECT, mode);
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if ( is_lba48 )
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{
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outport8(channel->port_base + REG_SECTOR_COUNT, count >> 8 & 0xFF);
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outport8(channel->port_base + REG_LBA_LOW, lba >> 24 & 0xFF);
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outport8(channel->port_base + REG_LBA_MID, lba >> 32 & 0xFF);
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outport8(channel->port_base + REG_LBA_HIGH, lba >> 40 & 0xFF);
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}
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outport8(channel->port_base + REG_SECTOR_COUNT, count >> 0 & 0xFF);
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outport8(channel->port_base + REG_LBA_LOW, lba >> 0 & 0xFF);
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outport8(channel->port_base + REG_LBA_MID, lba >> 8 & 0xFF);
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outport8(channel->port_base + REG_LBA_HIGH, lba >> 16 & 0xFF);
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}
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void Port::CommandDMA(uint8_t cmd, size_t size, bool write)
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{
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assert(size);
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assert(size <= Page::Size());
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assert(size <= UINT16_MAX);
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assert((size & 1) == 0); /* sizes and addresses must be 2-byte aligned */
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// Store the DMA region in the first PRD.
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prdt->physical = dma_physical_frame >> 0 & 0xFFFFFFFF;
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prdt->count = size;
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prdt->flags = PRD_FLAG_EOT;
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// Tell the hardware the location of the PRDT.
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uint32_t bm_prdt = control_physical_frame >> 0 & 0xFFFFFFFF;
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outport32(channel->busmaster_base + BUSMASTER_REG_PDRT, bm_prdt);
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// Clear the error and interrupt bits.
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uint8_t bm_status = inport8(channel->busmaster_base + BUSMASTER_REG_STATUS);
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bm_status |= BUSMASTER_STATUS_DMA_FAILURE | BUSMASTER_STATUS_INTERRUPT_PENDING;
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outport8(channel->busmaster_base + BUSMASTER_REG_STATUS, bm_status);
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// Set the transfer direction
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uint8_t bm_command = inport8(channel->busmaster_base + BUSMASTER_REG_COMMAND);
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if ( write )
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bm_command &= ~BUSMASTER_COMMAND_READING;
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else
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bm_command |= BUSMASTER_COMMAND_READING;
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outport8(channel->busmaster_base + BUSMASTER_REG_COMMAND, bm_command);
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// Anticipate we will be delivered an IRQ.
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PrepareAwaitInterrupt();
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transfer_in_progress = true;
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transfer_size = size;
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transfer_is_write = write;
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// Execute the command.
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outport8(channel->port_base + REG_COMMAND, cmd);
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// Start the DMA transfer.
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bm_command = inport8(channel->busmaster_base + BUSMASTER_REG_COMMAND);
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bm_command |= BUSMASTER_COMMAND_START;
|
|
outport8(channel->busmaster_base + BUSMASTER_REG_COMMAND, bm_command);
|
|
}
|
|
|
|
bool Port::FinishTransferDMA()
|
|
{
|
|
assert(transfer_in_progress);
|
|
|
|
bool result = true;
|
|
|
|
// Wait for an interrupt to arrive.
|
|
if ( !AwaitInterrupt(10000 /*ms*/) )
|
|
{
|
|
const char* op = transfer_is_write ? "write" : "read";
|
|
LogF("error: %s DMA timed out", op);
|
|
errno = EIO;
|
|
result = false;
|
|
// TODO: Is this a consistent state, do we need a reset, how to recover?
|
|
}
|
|
|
|
// Stop the DMA transfer.
|
|
uint8_t bm_command = inport8(channel->busmaster_base + BUSMASTER_REG_COMMAND);
|
|
bm_command &= ~BUSMASTER_COMMAND_START;
|
|
outport8(channel->busmaster_base + BUSMASTER_REG_COMMAND, bm_command);
|
|
|
|
// Clear the error and interrupt bits.
|
|
uint8_t bm_status = inport8(channel->busmaster_base + BUSMASTER_REG_STATUS);
|
|
uint8_t bm_set_flags = BUSMASTER_STATUS_DMA_FAILURE |
|
|
BUSMASTER_STATUS_INTERRUPT_PENDING;
|
|
outport8(channel->busmaster_base + BUSMASTER_REG_STATUS,
|
|
bm_status | bm_set_flags);
|
|
|
|
// Check if the DMA transfer failed.
|
|
if ( bm_status & BUSMASTER_STATUS_DMA_FAILURE )
|
|
{
|
|
const char* op = transfer_is_write ? "write" : "read";
|
|
LogF("error: %s DMA error", op);
|
|
errno = EIO;
|
|
result = false;
|
|
// TODO: Is this a consistent state, do we need a reset, how to recover?
|
|
}
|
|
|
|
transfer_in_progress = false;
|
|
return result;
|
|
}
|
|
|
|
void Port::CommandPIO(uint8_t cmd, size_t size, bool write)
|
|
{
|
|
assert(size);
|
|
assert(size <= Page::Size());
|
|
assert((size & 1) == 0); /* sizes and addresses must be 2-byte aligned */
|
|
|
|
// Anticipate we will be delivered an IRQ.
|
|
PrepareAwaitInterrupt();
|
|
|
|
// Execute the command.
|
|
(void) write;
|
|
outport8(channel->port_base + REG_COMMAND, cmd);
|
|
}
|
|
|
|
bool Port::TransferPIO(size_t size, bool write, bool no_error)
|
|
{
|
|
const char* op = write ? "write" : "read";
|
|
size_t i = 0;
|
|
while ( write || true )
|
|
{
|
|
if ( !write && i < size && !AwaitInterrupt(10000 /*ms*/) )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s timed out, waiting for transfer start", op);
|
|
return errno = EIO, false;
|
|
}
|
|
|
|
if ( !wait_inport8_clear(channel->port_base + REG_STATUS,
|
|
STATUS_BUSY, false, 10000 /*ms*/) )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s timed out waiting for transfer pre idle", op);
|
|
return errno = EIO, false;
|
|
}
|
|
|
|
uint8_t status = inport8(channel->port_base + REG_STATUS);
|
|
|
|
if ( status & STATUS_BUSY )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s unexpectedly still busy", op);
|
|
return errno = EIO, false;
|
|
}
|
|
|
|
if ( status & (STATUS_ERROR | STATUS_DRIVEFAULT) )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s error%s%s", op,
|
|
status & STATUS_ERROR ? " STATUS_ERROR" : "",
|
|
status & STATUS_DRIVEFAULT ? " STATUS_DRIVEFAULT" : "");
|
|
return errno = EIO, false;
|
|
}
|
|
|
|
if ( i == size )
|
|
break;
|
|
|
|
if ( !(status & STATUS_DATAREADY) )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s unexpectedly not ready", op);
|
|
return errno = EIO, false;
|
|
}
|
|
|
|
// Anticipate another IRQ if we're not at the end.
|
|
size_t i_sector_end = is_packet_interface ? i + size : i + block_size;
|
|
if ( (is_packet_interface && write) || i_sector_end != size )
|
|
PrepareAwaitInterrupt();
|
|
|
|
uint8_t* dma_data = (uint8_t*) dma_alloc.from;
|
|
|
|
if ( write )
|
|
{
|
|
while ( i < size && i < i_sector_end )
|
|
{
|
|
uint16_t value = dma_data[i + 0] << 0 | dma_data[i + 1] << 8;
|
|
outport16(channel->port_base + REG_DATA, value);
|
|
i += 2;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
while ( i < size && i < i_sector_end )
|
|
{
|
|
uint16_t value = inport16(channel->port_base + REG_DATA);
|
|
dma_data[i + 0] = (value >> 0) & 0xFF;
|
|
dma_data[i + 1] = (value >> 8) & 0xFF;
|
|
i += 2;
|
|
}
|
|
}
|
|
|
|
if ( write && !AwaitInterrupt(10000 /*ms*/) )
|
|
{
|
|
if ( !no_error )
|
|
LogF("error: %s timed out, waiting for transfer end", op);
|
|
return errno = EIO, false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
off_t Port::GetSize()
|
|
{
|
|
return device_size;
|
|
}
|
|
|
|
blkcnt_t Port::GetBlockCount()
|
|
{
|
|
return block_count;
|
|
}
|
|
|
|
blksize_t Port::GetBlockSize()
|
|
{
|
|
return block_size;
|
|
}
|
|
|
|
uint16_t Port::GetCylinderCount()
|
|
{
|
|
return cylinder_count;
|
|
}
|
|
|
|
uint16_t Port::GetHeadCount()
|
|
{
|
|
return head_count;
|
|
}
|
|
|
|
uint16_t Port::GetSectorCount()
|
|
{
|
|
return sector_count;
|
|
}
|
|
|
|
const char* Port::GetDriver()
|
|
{
|
|
return "ata";
|
|
}
|
|
|
|
const char* Port::GetModel()
|
|
{
|
|
return model;
|
|
}
|
|
|
|
const char* Port::GetSerial()
|
|
{
|
|
return serial;
|
|
}
|
|
|
|
const char* Port::GetRevision()
|
|
{
|
|
return revision;
|
|
}
|
|
|
|
const unsigned char* Port::GetATAIdentify(size_t* size_ptr)
|
|
{
|
|
return *size_ptr = sizeof(identify_data), identify_data;
|
|
}
|
|
|
|
int Port::sync(ioctx_t* ctx)
|
|
{
|
|
if ( is_packet_interface )
|
|
{
|
|
// TODO: SYNCHRONIZE CACHE 0x35
|
|
return errno = ENOSYS, -1;
|
|
}
|
|
(void) ctx;
|
|
ScopedLock lock(&channel->hw_lock);
|
|
channel->SelectDrive(port_index);
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return -1;
|
|
PrepareAwaitInterrupt();
|
|
uint8_t cmd = is_lba48 ? CMD_FLUSH_CACHE_EXT : CMD_FLUSH_CACHE;
|
|
outport8(channel->port_base + REG_COMMAND, cmd);
|
|
// TODO: This might take longer than 30 seconds according to the spec. But
|
|
// how long? Let's say twice that?
|
|
if ( !AwaitInterrupt(2 * 30000 /*ms*/) )
|
|
{
|
|
LogF("error: cache flush timed out");
|
|
transfer_in_progress = false;
|
|
return errno = EIO, -1;
|
|
}
|
|
transfer_in_progress = false;
|
|
uint8_t status = inport8(channel->port_base + REG_STATUS);
|
|
if ( status & (STATUS_ERROR | STATUS_DRIVEFAULT) )
|
|
{
|
|
LogF("error: IO error");
|
|
return errno = EIO, -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
ssize_t Port::pread(ioctx_t* ctx, unsigned char* buf, size_t count, off_t off)
|
|
{
|
|
if ( !block_size )
|
|
return errno = ENOMEDIUM, -1;
|
|
ssize_t result = 0;
|
|
while ( count )
|
|
{
|
|
ScopedLock lock(&channel->hw_lock);
|
|
channel->SelectDrive(port_index);
|
|
if ( device_size <= off )
|
|
break;
|
|
if ( (uintmax_t) device_size - off < (uintmax_t) count )
|
|
count = (size_t) device_size - off;
|
|
uintmax_t block_index = (uintmax_t) off / (uintmax_t) block_size;
|
|
uintmax_t block_offset = (uintmax_t) off % (uintmax_t) block_size;
|
|
uintmax_t amount = block_offset + count;
|
|
if ( Page::Size() < amount )
|
|
amount = Page::Size();
|
|
size_t num_blocks = (amount + block_size - 1) / block_size;
|
|
uintmax_t full_amount = num_blocks * block_size;
|
|
// If an asynchronous operation is in progress, let it finish.
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
unsigned char* dma_data = (unsigned char*) dma_alloc.from;
|
|
unsigned char* data = dma_data + block_offset;
|
|
size_t data_size = amount - block_offset;
|
|
if ( is_packet_interface )
|
|
{
|
|
struct atapi_packet* packet = (struct atapi_packet*) dma_alloc.from;
|
|
memset(packet, 0, sizeof(*packet));
|
|
packet->operation = ATAPI_CMD_READ;
|
|
packet->lba[0] = block_index >> 24 & 0xFF;
|
|
packet->lba[1] = block_index >> 16 & 0xFF;
|
|
packet->lba[2] = block_index >> 8 & 0xFF;
|
|
packet->lba[3] = block_index >> 0 & 0xFF;
|
|
packet->control = num_blocks;
|
|
if ( !CommandATAPI((size_t) full_amount) )
|
|
return result ? result : -1;
|
|
}
|
|
else
|
|
{
|
|
Seek(block_index, num_blocks);
|
|
if ( is_using_dma )
|
|
{
|
|
uint8_t cmd = is_lba48 ? CMD_READ_DMA_EXT : CMD_READ_DMA;
|
|
CommandDMA(cmd, (size_t) full_amount, false);
|
|
if ( !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
}
|
|
else
|
|
{
|
|
uint8_t cmd = is_lba48 ? CMD_READ_EXT : CMD_READ;
|
|
CommandPIO(cmd, (size_t) full_amount, false);
|
|
if ( !TransferPIO((size_t) full_amount, false) )
|
|
return result ? result : -1;
|
|
}
|
|
}
|
|
if ( !ctx->copy_to_dest(buf, data, data_size) )
|
|
return result ? result : -1;
|
|
buf += data_size;
|
|
count -= data_size;
|
|
result += data_size;
|
|
off += data_size;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
ssize_t Port::pwrite(ioctx_t* ctx, const unsigned char* buf, size_t count, off_t off)
|
|
{
|
|
if ( is_packet_interface )
|
|
return errno = EPERM, -1;
|
|
if ( !block_size )
|
|
return errno = ENOMEDIUM, -1;
|
|
ssize_t result = 0;
|
|
while ( count )
|
|
{
|
|
ScopedLock lock(&channel->hw_lock);
|
|
channel->SelectDrive(port_index);
|
|
if ( device_size <= off )
|
|
break;
|
|
if ( (uintmax_t) device_size - off < (uintmax_t) count )
|
|
count = (size_t) device_size - off;
|
|
uintmax_t block_index = (uintmax_t) off / (uintmax_t) block_size;
|
|
uintmax_t block_offset = (uintmax_t) off % (uintmax_t) block_size;
|
|
uintmax_t amount = block_offset + count;
|
|
if ( Page::Size() < amount )
|
|
amount = Page::Size();
|
|
size_t num_blocks = (amount + block_size - 1) / block_size;
|
|
uintmax_t full_amount = num_blocks * block_size;
|
|
// If an asynchronous operation is in progress, let it finish.
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
unsigned char* dma_data = (unsigned char*) dma_alloc.from;
|
|
unsigned char* data = dma_data + block_offset;
|
|
size_t data_size = amount - block_offset;
|
|
if ( block_offset || amount < full_amount )
|
|
{
|
|
if ( is_using_dma )
|
|
{
|
|
uint8_t cmd = is_lba48 ? CMD_READ_DMA_EXT : CMD_READ_DMA;
|
|
Seek(block_index, num_blocks);
|
|
CommandDMA(cmd, (size_t) full_amount, false);
|
|
if ( !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
}
|
|
else
|
|
{
|
|
uint8_t cmd = is_lba48 ? CMD_READ_EXT : CMD_READ;
|
|
Seek(block_index, num_blocks);
|
|
CommandPIO(cmd, (size_t) full_amount, false);
|
|
if ( !TransferPIO((size_t) full_amount, false) )
|
|
return result ? result : -1;
|
|
}
|
|
}
|
|
if ( !ctx->copy_from_src(data, buf, data_size) )
|
|
return result ? result : -1;
|
|
if ( is_using_dma )
|
|
{
|
|
Seek(block_index, num_blocks);
|
|
uint8_t cmd = is_lba48 ? CMD_WRITE_DMA_EXT : CMD_WRITE_DMA;
|
|
CommandDMA(cmd, (size_t) full_amount, true);
|
|
// Let the transfer finish asynchronously so the caller can prepare
|
|
// the next write operation to keep the write pipeline busy.
|
|
}
|
|
else
|
|
{
|
|
Seek(block_index, num_blocks);
|
|
uint8_t cmd = is_lba48 ? CMD_WRITE_EXT : CMD_WRITE;
|
|
CommandPIO(cmd, (size_t) full_amount, true);
|
|
if ( !TransferPIO((size_t) full_amount, true) )
|
|
return result ? result : -1;
|
|
}
|
|
buf += data_size;
|
|
count -= data_size;
|
|
result += data_size;
|
|
off += data_size;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
void Port::PrepareAwaitInterrupt()
|
|
{
|
|
interrupt_signaled = false;
|
|
}
|
|
|
|
bool Port::AwaitInterrupt(unsigned int msecs)
|
|
{
|
|
struct timespec timeout = timespec_make(msecs / 1000, (msecs % 1000) * 1000000L);
|
|
Clock* clock = Time::GetClock(CLOCK_BOOTTIME);
|
|
struct timespec begun;
|
|
clock->Get(&begun, NULL);
|
|
while ( true )
|
|
{
|
|
struct timespec now;
|
|
clock->Get(&now, NULL);
|
|
if ( interrupt_signaled )
|
|
return true;
|
|
struct timespec elapsed = timespec_sub(now, begun);
|
|
if ( timespec_le(timeout, elapsed) )
|
|
return errno = ETIMEDOUT, false;
|
|
// TODO: Can't safely back out here unless the pending operation is
|
|
// is properly cancelled.
|
|
//if ( Signal::IsPending() )
|
|
// return errno = EINTR, false;
|
|
kthread_yield();
|
|
}
|
|
}
|
|
|
|
void Port::OnInterrupt()
|
|
{
|
|
// Clear INTRQ.
|
|
uint8_t status = inport8(channel->port_base + REG_STATUS);
|
|
|
|
if ( status & STATUS_ERROR )
|
|
{
|
|
uint8_t error_status = inport8(channel->port_base + REG_ERROR);
|
|
(void) error_status; // TODO: How to handle this exactly?
|
|
}
|
|
|
|
if ( !interrupt_signaled )
|
|
{
|
|
interrupt_signaled = true;
|
|
// TODO: Priority schedule the blocking thread now.
|
|
}
|
|
}
|
|
|
|
} // namespace ATA
|
|
} // namespace Sortix
|