5980be9b3c
This work is based in part on code from NetBSD libm, libc and kernel. The library is partly public domain and partly BSD-style licensed.
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
/* $NetBSD: fpu.h,v 1.5 2008/04/16 21:51:03 cegger Exp $ */
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#ifndef _AMD64_FPU_H_
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#define _AMD64_FPU_H_
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/*
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* NetBSD/amd64 only uses the extended save/restore format used
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* by fxsave/fsrestore, to always deal with the SSE registers,
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* which are part of the ABI to pass floating point values.
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* Must be stored in memory on a 16-byte boundary.
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*/
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struct fxsave64 {
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__uint16_t fx_fcw;
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__uint16_t fx_fsw;
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__uint8_t fx_ftw;
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__uint8_t fx_unused1;
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__uint16_t fx_fop;
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__uint64_t fx_rip;
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__uint64_t fx_rdp;
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__uint32_t fx_mxcsr;
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__uint32_t fx_mxcsr_mask;
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__uint64_t fx_st[8][2]; /* 8 normal FP regs */
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__uint64_t fx_xmm[16][2]; /* 16 SSE2 registers */
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__uint8_t fx_unused3[96];
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} __attribute__((__packed__));
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struct savefpu {
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struct fxsave64 fp_fxsave; /* see above */
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__uint16_t fp_ex_sw; /* saved status from last exception */
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__uint16_t fp_ex_tw; /* saved tag from last exception */
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} __attribute__((__aligned__(16)));
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/*
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* The i387 defaults to Intel extended precision mode and round to nearest,
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* with all exceptions masked.
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*/
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#define __INITIAL_NPXCW__ 0x037f
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#define __INITIAL_MXCSR__ 0x1f80
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#define __INITIAL_MXCSR_MASK__ 0xffbf
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/* NetBSD uses IEEE double precision. */
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#define __NetBSD_NPXCW__ 0x127f
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/* Linux just uses the default control word. */
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#define __Linux_NPXCW__ 0x037f
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#endif /* _AMD64_FPU_H_ */
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